1. Field of the Invention
The present invention relates to a delay line, and particularly to, for example, a centralized, constant-type delay line.
2. Description of the Prior Art
FIG. 11 is an illustrative view showing an example of a conventional delay line serving as a background of the present invention. The delay line 1 includes a printed board 2. On one surface of the printed board 2, for example, a ferrite inductor 3 is fixed. Moreover, onto the other surface of the printed board 2, a chip capacitor 4 is soldered. The ferrite inductor 3 and the chip capacitor 4 are connected by a pattern electrode formed on the printed board 2. A circuit formed by the ferrite inductor 3 and the chip capacitor 4 is connected to a terminal 5 extending from the printed board 2.
In the delay line 1, as shown in FIG. 12, a plural number of inductances are formed by the ferrite inductor 3, and a plural number of capacitances are formed by the chip capacitor 4. The delay line is formed by these inductances and capacitances.
However, there is about 20% variation in the inductance of the ferrite inductor used in such a delay line, causing variations in a delay time of the delay line. Because the ferrite inductor and the chip capacitor are exposed, the inductance and the capacitance fluctuate by variations of the atmospheric temperature. And hence, temperature characteristics of the delay line also change. Moreover, since such delay lines include terminals, it is difficult to meet a recent, surface mounting demand.